Algorithms for scalable synchronization on shared-memory multiprocessors.
Fastlane performance software#
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. Deadline-aware scheduling for software transactional memory. Efficient synchronization of multiprocessors with shared memory. Morgan and Claypool Publishers, December 2010. On the correctness of transactional memory. Lock-free and scalable multi-version software transactional memory. Dynamic performance tuning of word-based software transactional memory. NOrec: Streamlining STM by abolishing ownership records.
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Fastlane performance code#
The runtime system selects the code path providing the best throughput, depending on the number of cores available on the target machine. Multiple code paths are produced for execution on a single, few, and many cores. We implement FastLane as an extension of a state-of-the-art STM runtime system and compiler.
![fastlane performance fastlane performance](https://i.ytimg.com/vi/zwLFtWpoSLQ/maxresdefault.jpg)
Helpers thus contribute to the application progress without impairing on the performance of the master. We introduce a novel algorithm that differentiates between two types of threads: One thread (the master) executes transactions pessimistically without ever aborting, thus with minimal instrumentation and management costs, while other threads (the helpers) can commit speculative transactions only when they do not conflict with the master. FastLane seeks to reduce instrumentation costs and thus performance degradation in its target operation range.
![fastlane performance fastlane performance](https://jbswhiskey.com/wp-content/uploads/2019/04/jb_whiskeycreek_fastlane_fb_ad.jpg)
In this paper, we propose FastLane, a new STM algorithm that bridges the performance gap between sequential execution and classical STM algorithms when running on few cores. This often leads STM-based programs with low thread counts to perform worse than a sequential, non-instrumented version of the same application. However, the absolute performance is typically impaired by the overheads of transaction management and instrumented accesses to shared memory. Software transactional memory (STM) can lead to scalable implementations of concurrent programs, as the relative performance of an application increases with the number of threads that support it.